Condor Currents

SMEPilot: Characterizing and Optimizing LLM Inference...

Condor Currents ·

2026/06/18

## Episode SummaryIn this episode, we cover: - **SMEPilot: Characterizing and Optimizing LLM Inference with Scalable Matrix Extensions** (arXiv) - **The Price of Anarchy in Disaggregated Inference** (arXiv) - **RISC-V Mentorship Taught Me the RISC-V ISA Is Far More Than a Reference Manual** (riscv_news) - **One ISA, Infinite Use Cases: RISC-V and the Road to Workload-Specific Silicon** (riscv_news) - **RISC-V set to announce 25% market penetration — open-standard ISA is ahead of schedule, securing

en-us

A Spatio-Temporal Expert Prefetching Framework for...

Condor Currents ·

2026/06/17

## Episode SummaryIn this episode, we cover: - **A Spatio-Temporal Expert Prefetching Framework for Efficient MoE-based LLM Inference** (arXiv) - **MADAR: An Address-Free Processor** (arXiv) - **Checking In On The ISA Wars And Its Impact On CPU Architectures - Hackaday** (google_arch) - **Support RAJA and Scientific Applications on RVV Architectures** (riscv_news) - **Synergy Quantum Unveils Quantum-Safe Silicon IP Cores for RISC-V-Based SoCs - PR Newswire** (google_riscv) --- *Sponsored by

en-us

Tiara: A Programmable Line-Rate ISA for Remote Memory...

Condor Currents ·

2026/06/14

## Episode SummaryIn this episode, we cover: - **Tiara: A Programmable Line-Rate ISA for Remote Memory Access** (arXiv) - **HierSVA: A Data Synthesis Pipeline, Dataset, and Benchmark for LLM-Driven Hierarchical Hardware Formal Verification** (arXiv) - **Using a Performance Model to Implement a Superscalar CVA6** (riscv_news) - **Ben C.'s Clever Compiler Imports Verilog Designs, Including a Working RISC-V CPU, Into Factorio - Hackster.io** (google_riscv) - **Now you can put a SpacemiT K3 RISC-V

en-us

Isolation-aware Scheduling Framework for DNN-based...

Condor Currents ·

2026/06/13

## Episode Summary In this episode, we cover: - **Isolation-aware Scheduling Framework for DNN-based End-to-End Autonomous Driving System on Tile-based Accelerators** (arXiv) - **Non-Parametric Dual-Manifold Mapping via 8-Bit Bounded Transformation Matrices: Challenging FP-centric Hardware Paradigms in Low-Energy AI** (arXiv) - **160-core RISC V Board Is The M.2 CoProcessor You Didn’t Know You Needed - Hackaday** (google_riscv) - **Microchip Upgrades Its Mi-V RV32 RISC-V Soft-Core Processor,

en-us

Energy-Efficient On-Device RAG on a Mobile NPU:...

Condor Currents ·

2026/06/12

## Episode Summary In this episode, we cover: - **Energy-Efficient On-Device RAG on a Mobile NPU: System Design and Benchmark on Snapdragon X Elite** (arXiv) - **A Hybrid Edge-Cloud Architecture for Low-Latency Entitlement Verification in Resource-Constrained Devices** (arXiv) - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - TechPowerUp** (google_riscv) - **Security Researchers Find Current RISC-V CPU Implementations Coming Up Short - Phoronix**

en-us

SupraSNN: Exploiting Synapse-Level Parallelism in...

Condor Currents ·

2026/06/11

## Episode SummaryIn this episode, we cover: - **SupraSNN: Exploiting Synapse-Level Parallelism in Spiking Neural Network Accelerators through Co-Optimized Mapping and Scheduling** (arXiv) - **Partitioned Tags, Shared Data: Reconciling Strict Cache Isolation with Write-Shared Coherence** (arXiv) - **Intel Panther Lake Technical Deep Dive - Compute Tile: CPU Architecture - TechPowerUp** (google_arch) - **Fortior FU75xx dual-core motor control MCU family combines 32-bit RISC-V core with 2nd-gen Motor

en-us

NextSilicon to Productize Arbel RISC-V Core Into...

Condor Currents ·

2026/06/10

## Episode SummaryIn this episode, we cover: - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - Business Wire** (google_riscv) - **NextSilicon Productizes Arbel RISC-V Core Into 64-Core Enterprise Processor - Quantum Zeitgeist** (google_riscv) - **NextSilicon Productizes Arbel RISC-V Core Into 64-Core Enterprise Processor - Quantum Zeitgeist** (google_arch) - **NextSilicon to Productize Arbel RISC-V Core into 64-Core Enterprise Processor for AI and

en-us

Toward Intelligent Prefetching: A Survey on Complex...

Condor Currents ·

2026/06/09

## Episode SummaryIn this episode, we cover: - **Toward Intelligent Prefetching: A Survey on Complex Memory Access Prediction Techniques** (arXiv) - **SPARX: Secure and Privacy-Aware Approximate CNN Acceleration with Edge RISC-V SoC** (arXiv) - **The RISC-V Vector Extensions for AI - Jon Peddie Research** (google_riscv) - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - The National Law Review** (google_riscv) - **NextSilicon to Productize Arbel

en-us

MOSAIC: A Workload-Driven Simulation and Design-Space...

Condor Currents ·

2026/06/08

## Episode SummaryIn this episode, we cover: - **MOSAIC: A Workload-Driven Simulation and Design-Space Exploration Framework for Heterogeneous NPUs** (arXiv) - **NetKV: Network-Aware Decode Instance Selection for Disaggregated LLM Inference** (arXiv) - **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_arch) - **As Alibaba launches server-grade RISC-V CPU, Beijing throws its weight behind ISA - The Register** (google_riscv) - **Vortex 3.0 Released As Full-Stack,

en-us

ANNS-AMP: Accelerating Approximate Nearest Neighbor...

Condor Currents ·

2026/06/07

## Episode Summary In this episode, we cover: - **ANNS-AMP: Accelerating Approximate Nearest Neighbor Search via Adaptive Mixed-Precision Computing** (arXiv) - **MOSAIC: A Workload-Driven Simulation and Design-Space Exploration Framework for Heterogeneous NPUs** (arXiv) - **Evaluating and Calibrating Performance On RISC-V Vector Processors (KTH, LLNL, BSC) - Semiconductor Engineering** (google_riscv) - **Breker Verification Systems and Frontgrade Gaisler Collaborate on High-Reliability RISC-V Fault

en-us

BIDENT: Heterogeneous Operator-level Mapping for...

Condor Currents ·

2026/06/06

## Episode Summary In this episode, we cover: - **BIDENT: Heterogeneous Operator-level Mapping for Efficient Edge Inference** (arXiv) - **Multi-Segment Attention: Enabling Efficient KV-Cache Management for Faster Large Language Model Serving** (arXiv) - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - Phoronix** (google_riscv) - **A Deep Dive Into CPU Architecture - i-programmer.info** (google_arch) - **India Launches DHRUV64, Its First 1 GHz, 64-bit Dual-Core RISC-V

en-us

AheadComputing Introduces Breakthrough CPU...

Condor Currents ·

2026/06/05

## Episode SummaryIn this episode, we cover: - **AheadComputing Introduces Breakthrough CPU Architecture for General-Purpose Computing, With Jim Keller on Board - TechPowerUp** (google_arch) - **Deja Vu: A Brief History of Every Mac CPU Architecture - How-To Geek** (google_arch) - **How RISC-V CPUs and GPUs Are Reshaping High-Performance SoCs in 2026 - News and Statistics - IndexBox** (google_riscv) - **How Did An AI Agent Build a RISC V CPU Core In Just 12 Hours - IEEE Spectrum** (google_riscv) -

en-us

Migration Using Context Cache for Multicore RISC‐V...

Condor Currents ·

2026/06/04

## Episode Summary In this episode, we cover: - **Migration Using Context Cache for Multicore RISC‐V Processor - Wiley Online Library** (google_riscv) - **The Evolution of CPU Architectures – From Intel 4004 To Modern SoCs - Wccftech** (google_arch) - **Performance aware shared memory hierarchy model for multicore processors - Nature** (google_arch) - **RISC-V vs ARM: Which Instruction Set Architecture Will Dominate the Future? - Electropages** (google_arch) - **Bit-Brick K1: Raspberry Pi 5

en-us

Dead on Arrival: Characterizing and Protecting...

Condor Currents ·

2026/06/03

## Episode Summary In this episode, we cover: - **Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures** (arXiv) - **CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees** (arXiv) - **The key CPU architecture you've never heard of: RISC-V - Red Shark News** (google_arch) - **RISC-V Vector Extension: Between standardization and tailor-made accelerators - eeNews

en-us

RISC-V set to announce 25% market penetration —...

Condor Currents ·

2026/06/02

## Episode Summary In this episode, we cover: - **RISC-V set to announce 25% market penetration — open-standard ISA is ahead of schedule, securing fast-growing silicon footprint - Tom's Hardware** (google_riscv) - **Nvidia's CUDA platform now supports RISC-V — support brings open source instruction set to AI platforms, joining x86 and Arm - Tom's Hardware** (google_riscv) - **White paper: The All-Big-Core CPU Architecture of MediaTek Dimensity 9300 - MediaTek** (google_arch) - **QuMA: Researchers

en-us

Regular-Dead on Arrival: Characterizing and...

Condor Currents ·

2026/06/01

## Episode Summary In this episode, we cover: - **Regular-Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures** (arXiv) - **Observation, Not Prediction: Conversation-Level Disaggregated Scheduling for Agentic Serving** (arXiv) - **SpacemiT K3 “16-core” RISC-V SoC system information and (early) benchmarks - CNX Software** (google_riscv) - **RISC-V Mentorship Taught Me the RISC-V ISA Is Far More Than a Reference Manual** (riscv_news) - **One ISA,

en-us

FREESS: A Web-Based Educational Simulator for a...

Condor Currents ·

2026/05/31

## Episode Summary In this episode, we cover: - **FREESS: A Web-Based Educational Simulator for a RISC-V-Inspired Superscalar Processor with Tomasulo-Style Dynamic Scheduling** (arXiv) - **Code size reduction by advanced near addressing modes** (arXiv) - **Evaluating RISC-V Vector Processors: GCC vs. LLVM Autovectorization Benchmarks (May 2026) - News and Statistics - IndexBox** (google_riscv) - **Checking In On The ISA Wars And Its Impact On CPU Architectures - Hackaday** (google_arch) - **Support

en-us

Co-Designing Graph-based Approximate Nearest Neighbor...

Condor Currents ·

2026/05/30

## Episode Summary In this episode, we cover: - **Co-Designing Graph-based Approximate Nearest Neighbor Search at Billion Scale for Processing-in-Memory** (arXiv) - **Code size reduction by advanced near addressing modes** (arXiv) - **AI agent designs complete RISC-V CPU core autonomously - MSN** (google_riscv) - **CPU Instruction Set Architecture (ISA) Market - Market Growth Reports** (google_arch) - **Using a Performance Model to Implement a Superscalar CVA6** (riscv_news) --- *Sponsored by

en-us

Sustainable Real-Time 8K60 HEVC Encoding for V2X:...

Condor Currents ·

2026/05/24

## Episode SummaryIn this episode, we cover: - **Sustainable Real-Time 8K60 HEVC Encoding for V2X: Repurposing Legacy NVENC Hardware at the Vehicular Edge** (arXiv) - **PoisonCap: Efficient Hierarchical Temporal Safety for CHERI** (arXiv) - **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_riscv) - **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_arch) - **The RISC-V Vector Extensions for AI - Jon Peddie Research**

en-us

Accelerating State-Vector Quantum Simulation on...

Condor Currents ·

2026/05/23

## Episode Summary In this episode, we cover: - **Accelerating State-Vector Quantum Simulation on Integrated GPUs via Cache Locality Optimization: A Cross-Architecture Evaluation** (arXiv) - **NasZip: Software and Hardware Co-Design to Accelerate Approximate Nearest Neighbor Search with DIMM-Based Near-Data Processing** (arXiv) - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - Phoronix** (google_riscv) - **A Deep Dive Into CPU Architecture - i-programmer.info**

en-us

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