Condor Currents

RAGMark: A Comprehensive Framework for Benchmarking...

Condor Currents ·

2026/09/08

## Episode SummaryIn this episode, we cover: - **RAGMark: A Comprehensive Framework for Benchmarking Retrieval-Augmented Generation Systems** (arXiv) - **AutoUVM: Automated Prefetching Framework for LLMs under UVM Oversubscription** (arXiv) - **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_arch) - **RISC-V extensions for high performance embedded computing ... - eeNews Europe** (google_riscv) - **How Did An AI Agent Build a RISC V CPU Core In Just 12 Hours -

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GreenPipe: Power Modeling for Containerized DNN...

Condor Currents ·

2026/09/07

## Episode SummaryIn this episode, we cover: - **GreenPipe: Power Modeling for Containerized DNN Inference on Kubernetes Edge Nodes** (arXiv) - **A Time-Encoded Analog Photonic Interposer for Energy-EfficientIntegration of Analog Vision Sensors and Analog Accelerators** (arXiv) - **The RISC-V Vector Extensions for AI - Jon Peddie Research** (google_riscv) - **AheadComputing Inc. Raises Additional $30M Seed2 Round to Reimagine CPU Architecture - hpcwire.com** (google_arch) - **AheadComputing

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Confidence-Gated Admission for Hardware Prefetching:...

Condor Currents ·

2026/09/06

## Episode Summary In this episode, we cover: - **Confidence-Gated Admission for Hardware Prefetching: When the Gate Matters More Than the Predictor** (arXiv) - **Quality Recovery for Quantized KV Caches via Low-Rank Attention Adaptation** (arXiv) - **AheadComputing Inc. Raises Additional $30M Seed2 Round to Reimagine CPU Architecture - HPCwire** (google_arch) - **AheadComputing Introduces Breakthrough CPU Architecture for General-Purpose Computing, With Jim Keller on Board - TechPowerUp**

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A single-precision floating-point systolic Givens-QRD...

Condor Currents ·

2026/09/05

## Episode SummaryIn this episode, we cover: - **A single-precision floating-point systolic Givens-QRD Triangular Solver for MVDR Beamforming** (arXiv) - **FFSlim: An Efficient and Lightweight Format for Multi-modal Data Storage and Retrieval** (arXiv) - **QuMA: Researchers Develop Quantum Microarchitecture that "Bridges the Gap" in Processor System Stacks - IEEE Computer Society** (google_arch) - **Performance aware shared memory hierarchy model for multicore processors - Nature** (google_arch) -

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Confidence-Gated Admission for Hardware Prefetching:...

Condor Currents ·

2026/09/04

## Episode SummaryIn this episode, we cover: - **Confidence-Gated Admission for Hardware Prefetching: When the Gate Matters More Than the Predictor** (arXiv) - **Para-Pipe: Exploiting Hierarchical Operator Parallelism of ML Computational Graphs on SoCs** (arXiv) - **RISC-V: The Open-Source Revolution in CPU Architecture - design-reuse.com** (google_arch) - **The Evolution of CPU Architectures – From Intel 4004 To Modern SoCs - wccftech.com** (google_arch) - **RISC-V vs ARM: Which Instruction Set

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The key CPU architecture you've never heard of:...

Condor Currents ·

2026/09/03

## Episode SummaryIn this episode, we cover: - **The key CPU architecture you've never heard of: RISC-V - redsharknews.com** (google_arch) - **Checking In On The ISA Wars And Its Impact On CPU Architectures - hackaday.com** (google_arch) - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - phoronix.com** (google_riscv) - **RISC-V Targets Data Centers as Open ISA Pushes Beyond Embedded Systems - EE Times Asia** (google_riscv) - **Migration Using Context Cache for

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SchedBlame: Who Ran While You Waited?...

Condor Currents ·

2026/09/02

## Episode SummaryIn this episode, we cover: - **SchedBlame: Who Ran While You Waited? Culprit-Attributed CPU Contention for Containers on Stock Kernels** (arXiv) - **HBQ: Hierarchical Scaling Block Quantization with Hardware-Efficiency-Aware Design for Accurate LLM Inference** (arXiv) - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - techpowerup.com** (google_riscv) - **Ultra-compact mini PC from Japanese maker packs 8-core RISC-V CPU and up to 32

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Performance Characterization of SPEC CPU 2026 on AMD...

Condor Currents ·

2026/09/01

## Episode SummaryIn this episode, we cover: - **Performance Characterization of SPEC CPU 2026 on AMD EPYC 9755 Processor** (arXiv) - **Hardware Acceleration of Block-Diffusion LLM for Edge Devices** (arXiv) - **Migration Using Context Cache for Multicore RISC‐V Processor - onlinelibrary.wiley.com** (google_riscv) - **QuMA: Researchers Develop Quantum Microarchitecture that "Bridges the Gap" in Processor System Stacks - computer.org** (google_arch) - **A Deep Dive Into CPU Architecture -

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CHIPSMORE: Compute-in-Interconnect and -Memory...

Condor Currents ·

2026/08/31

## Episode SummaryIn this episode, we cover: - **CHIPSMORE: Compute-in-Interconnect and -Memory Chiplets for Multi-Mode Multi-Request LLM Inference Acceleration** (arXiv) - **Scalable AXI4 Transaction Monitoring for Mixed-Criticality SoCs: From Phase-Level Precision to ID-Level Efficiency** (arXiv) - **Checking In On The ISA Wars And Its Impact On CPU Architectures - Hackaday** (google_arch) - **The Evolution of CPU Architectures – From Intel 4004 To Modern SoCs - Wccftech** (google_arch) -

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Great Expectations: Benchmarking the Real-World...

Condor Currents ·

2026/08/30

## Episode Summary In this episode, we cover: - **Great Expectations: Benchmarking the Real-World Performance of RVV 1.0 in HPC** (arXiv) - **AI Hardware Accelerators for Large Language Models: Architectures and the Memory Wall** (arXiv) - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - Phoronix** (google_riscv) - **RISC-V Soft Processor System on DE10-Lite - Hackster.io** (google_riscv) - **The next RISC-V processor frontier: AI - EDN - Voice of the Engineer**

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NOVA: Technology-Architecture Co-Design of...

Condor Currents ·

2026/08/29

## Episode Summary In this episode, we cover: - **NOVA: Technology-Architecture Co-Design of Near-Memory Processing for Attention-SSM-MoE Hybrid LLM Inference** (arXiv) - **Performance Foundations of Parallel & Distributed Reasoning Language Models** (arXiv) - **Nvidia Vera CPU Architecture: Max single-threaded CPU at scale for agents - GamesBeat** (google_arch) - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - Business Wire** (google_riscv) -

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SILK: Closing the Time-of-Check-to-Time-of-Use Gap in...

Condor Currents ·

2026/08/28

## Episode SummaryIn this episode, we cover: - **SILK: Closing the Time-of-Check-to-Time-of-Use Gap in RoT-Protected AI Systems** (arXiv) - **Simthesizer: An Agent-Driven Simulation Framework for LLM Serving Systems** (arXiv) - **Design of a low-power RISC-V based intelligent endoscopy detection processor: EndoRISC-V - nature.com** (google_riscv) - **Enabling Comprehensive CWE-based Assurance for RISC-V Processors - Semiconductor Engineering** (google_riscv) - **Milk-V Jupiter2 is mini PC with a

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PRO-RAN: Processor-Level Characterization of Open RAN...

Condor Currents ·

2026/08/27

## Episode SummaryIn this episode, we cover: - **PRO-RAN: Processor-Level Characterization of Open RAN Centralized and Distributed Units** (arXiv) - **FoldPipe: Bounded Remote Streaming of Native Molecular Shards with Asynchronous Prefetch** (arXiv) - **China's LineShine tops supercomputer ranking with all-CPU architecture - China Daily** (google_arch) - **SpacemiT to launch server-class RISC-V processor following capital injection - South China Morning Post** (google_riscv) - **AI is

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FLINT: Efficiently Leveraging High Bandwidth Flash...

Condor Currents ·

2026/08/26

## Episode SummaryIn this episode, we cover: - **FLINT: Efficiently Leveraging High Bandwidth Flash for Capacity-Scalable LLM Inference Acceleration** (arXiv) - **Squeezing the Cache, Preserving the Truth: Monotonic Equipotential Allocation with Geodesia-KV** (arXiv) - **How Cache Coherency Simplifies AI Software** (semiengineering) - **Arm Reveals AGI Server CPU Architecture at Hot Chips, Targeting Agentic AI Workloads - finance.biggo.com** (google_arch) - **Security Researchers Find Current

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Pipeline-Native Transformers: Co-Designing Model...

Condor Currents ·

2026/08/25

## Episode SummaryIn this episode, we cover: - **Pipeline-Native Transformers: Co-Designing Model Architecture and CPU Inference for Bandwidth-Efficient Autoregressive Decode** (arXiv) - **Elastic KV Cache for LLM Serving:A Working Reclamation Mechanism, and Why Chunked Prefill Already Closes the Gap** (arXiv) - **Design of a low-power RISC-V based intelligent endoscopy detection processor: EndoRISC-V - Nature** (google_riscv) - **Prompt to tape out: Autonomous AI agent builds 1.5 GHz RISC-V CPU -

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Architecting the Next Generation of Asynchronous,...

Condor Currents ·

2026/08/24

## Episode SummaryIn this episode, we cover: - **Architecting the Next Generation of Asynchronous, Distributed GPUs for the AI Era** (arXiv) - **TreeWY: Speculative Verification for Gated DeltaNet Hybrids** (arXiv) - **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_arch) - **RISC-V extensions for high performance embedded computing ... - eeNews Europe** (google_riscv) - **RISC-V CPU Performance Up 8x In Five Years: SiFive HiFive Unmatched To SpacemiT K3 -

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SPICE: Speculative Prefetching with Low-Rank Expert...

Condor Currents ·

2026/08/23

## Episode Summary In this episode, we cover: - **SPICE: Speculative Prefetching with Low-Rank Expert Surrogates and Heterogeneous Orchestration for MoE Inference Acceleration** (arXiv) - **Assessing Triple Modular Redundancy for Wide-Link, Low-Latency NoC Routers: Reliability and Physical Design Challenges** (arXiv) - **The RISC-V Vector Extensions for AI - Jon Peddie Research** (google_riscv) - **StarFive Dubhe-100 – A 64-bit, RVA23-compliant RISC-V core for high-performance applications - CNX

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Formal Performance and Compile Time Guarantees for...

Condor Currents ·

2026/08/22

## Episode SummaryIn this episode, we cover: - **Formal Performance and Compile Time Guarantees for Compiler Optimization Heuristics** (arXiv) - **Beyond Binary Priorities: Multi-Tier SLA Scheduling for Large Language Model Serving** (arXiv) - **AheadComputing Introduces Breakthrough CPU Architecture for General-Purpose Computing, With Jim Keller on Board - TechPowerUp** (google_arch) - **Deja Vu: A Brief History of Every Mac CPU Architecture - How-To Geek** (google_arch) - **Linux Kernel 7.2

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From Retrieved Context to Runtime Control: Adaptive...

Condor Currents ·

2026/08/21

## Episode Summary In this episode, we cover: - **From Retrieved Context to Runtime Control: Adaptive Compression for Edge-based RAG** (arXiv) - **DTX: A Throughput-First Training Accelerator for Diffusion and Transformer Models** (arXiv) - **SpacemiT K3 “16-core” RISC-V SoC system information and (early) benchmarks - CNX Software** (google_riscv) - **NextSilicon Productizes Arbel RISC-V Core Into 64-Core Enterprise Processor - Quantum Zeitgeist** (google_arch) - **Using a Performance Model to

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A Thread-Register Decoupled GPU Execution Model for...

Condor Currents ·

2026/08/20

## Episode SummaryIn this episode, we cover: - **A Thread-Register Decoupled GPU Execution Model for Efficient Tensor Computation** (arXiv) - **Performance Verification of the AmpereOne CPU Core** (arXiv) - **Intel says Nova Lake, its next major CPU architecture, is coming to desktop PCs before servers - TechSpot** (google_arch) - **Bit-Brick K1: Raspberry Pi 5 alternative with different CPU architecture, M.2 and PCIe support launches - Notebookcheck** (google_arch) - **India unveils a homegrown

en-us

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