Condor Currents

FPGA Lifecycle Management for RISC-V Systems

Condor Currents ·

2026/08/19

## Episode SummaryIn this episode, we cover: - **FPGA Lifecycle Management for RISC-V Systems** (arXiv) - **CTTE: An Open Dual-Protocol RISC-V Trace Encoder for N-Trace and E-Trace** (arXiv) - **Migration Using Context Cache for Multicore RISC‐V Processor - Wiley Online Library** (google_riscv) - **RISC-V vs ARM: Which Instruction Set Architecture Will Dominate the Future? - Electropages** (google_arch) - **Performance aware shared memory hierarchy model for multicore processors - Nature**

en-us

ETHEREAL: A 25.6-$μ$s/inf. Low-latency Event-driven...

Condor Currents ·

2026/08/18

## Episode SummaryIn this episode, we cover: - **ETHEREAL: A 25.6-$μ$s/inf. Low-latency Event-driven Graph-neural-network Processor for High-resolution Vision at the Edge** (arXiv) - **Dryas: A Reprogrammable Engine for High-Speed Interconnect Tracing and Analysis** (arXiv) - **The RISC-V Vector Extensions for AI - jonpeddie.com** (google_riscv) - **The Evolution of CPU Architectures – From Intel 4004 To Modern SoCs - wccftech.com** (google_arch) - **QuMA: Researchers Develop Quantum

en-us

Testing the EPYC Conjecture on Real Hardware:...

Condor Currents ·

2026/08/17

## Episode SummaryIn this episode, we cover: - **Testing the EPYC Conjecture on Real Hardware: MoA-Guided Dense Matrix Multiplication on NCSA Delta (AMD EPYC 7763 Milan)** (arXiv) - **Beyond Capacity: Scalable MoE LLM Inference via High-Bandwidth Flash with Direct GPU and HBM Paths** (arXiv) - **RISC-V Mentorship Taught Me the RISC-V ISA Is Far More Than a Reference Manual** (riscv_news) - **AheadComputing Introduces Breakthrough CPU Architecture for General-Purpose Computing, With Jim Keller on

en-us

SLAC: Access-Driven CPU-to-GPU Side-channel Attacks...

Condor Currents ·

2026/08/16

## Episode Summary In this episode, we cover: - **SLAC: Access-Driven CPU-to-GPU Side-channel Attacks via System-Level Cache on Apple Silicon** (arXiv) - **Potential Applications of HBF in LLM Serving Systems** (arXiv) - **Checking In On The ISA Wars And Its Impact On CPU Architectures - Hackaday** (google_arch) - **Support RAJA and Scientific Applications on RVV Architectures** (riscv_news) - **Zhihe A210 octa-core RISC-V SoC with 12 TOPS NPU powers SoM-based development board - CNX Software**

en-us

What Actually Serializes GPU LZ77 Decode: Three...

Condor Currents ·

2026/08/15

## Episode SummaryIn this episode, we cover: - **What Actually Serializes GPU LZ77 Decode: Three Decoders, Three Mechanisms, and an Encode-Time Lever That Removes the Last One** (arXiv) - **ARMOR: Accelerating RTL Simulation by Mitigating the Front-End Bottleneck Using Node Compression** (arXiv) - **SpacemiT K3 “16-core” RISC-V SoC system information and (early) benchmarks - cnx-software.com** (google_riscv) - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX -

en-us

SLAC: Access-Driven CPU-to-GPU Side-channel Attacks...

Condor Currents ·

2026/08/14

## Episode Summary In this episode, we cover: - **SLAC: Access-Driven CPU-to-GPU Side-channel Attacks via System-Level Cache on Apple Silicon** (arXiv) - **DistillCache: KL-Guided Adaptive KV-Cache Eviction for Memory-Efficient LLM Inference** (arXiv) - **A Deep Dive Into CPU Architecture - i-programmer.info** (google_arch) - **How Did An AI Agent Build a RISC V CPU Core In Just 12 Hours - IEEE Spectrum** (google_riscv) - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise

en-us

Why Do Prefetchers Fail? Let Agents Answer

Condor Currents ·

2026/08/13

## Episode SummaryIn this episode, we cover: - **Why Do Prefetchers Fail? Let Agents Answer** (arXiv) - **Machine Shape and Hierarchical Blocking: A Mathematics of Arrays Formalization, with an Open Problem in Hierarchical Shape Occupancy** (arXiv) - **Checking In On The ISA Wars And Its Impact On CPU Architectures - hackaday.com** (google_arch) - **China's LineShine tops supercomputer ranking with all-CPU architecture - chinadaily.com.cn** (google_arch) - **QuMA: Researchers Develop Quantum

en-us

APEX: Adaptive Expert Prefetching for...

Condor Currents ·

2026/08/12

## Episode SummaryIn this episode, we cover: - **APEX: Adaptive Expert Prefetching for Memory-Efficient Edge MoE Inference** (arXiv) - **Aneto: Predicting System Performance by Exploiting Cross-Workload Regularity** (arXiv) - **RISC-V: The Open-Source Revolution in CPU Architecture - design-reuse.com** (google_arch) - **Conflict to Compliance: RISC-V Extension Migration Across Spec, HW, and SW** (riscv_news) - **China's LineShine tops supercomputer ranking with all-CPU architecture - China Daily**

en-us

ArchAgent v2: A Case Study with the Data Prefetching...

Condor Currents ·

2026/08/11

## Episode Summary In this episode, we cover: - **ArchAgent v2: A Case Study with the Data Prefetching Championship** (arXiv) - **The Fallacy of Independent Ceilings: Characterizing Coupled Load-Branch Stall Interaction** (arXiv) - **Migration Using Context Cache for Multicore RISC‐V Processor - onlinelibrary.wiley.com** (google_riscv) - **Chinese Loongson processors have leaky caches, researchers find** (the_register) - **Spectre rears its ugly head again as researchers show some RISC-V chips are

en-us

A Centralized Performance Monitoring Architecture for...

Condor Currents ·

2026/08/08

## Episode SummaryIn this episode, we cover: - **A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs** (arXiv) - **MCHA: A Memory-Centric Hierarchical Architecture for Parallel-Sequential Computing** (arXiv) - **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_arch) - **Evaluating and Calibrating Performance On RISC-V Vector Processors (KTH, LLNL, BSC) - semiengineering.com** (google_riscv) - **The RISC-V Vector Extensions for AI -

en-us

Heterogeneous LLM Serving with General-Purpose...

Condor Currents ·

2026/08/07

## Episode Summary In this episode, we cover: - **Heterogeneous LLM Serving with General-Purpose Processing-Near-Memory for Retrieval-Based Sparse Attention** (arXiv) - **Celty: SpMspV GPU Kernel and SIMT Co-Design for Efficient Dual-Sparse LLM Inference** (arXiv) - **Bit-Brick K1: Raspberry Pi 5 alternative with different CPU architecture, M.2 and PCIe support launches - notebookcheck.net** (google_arch) - **AheadComputing Introduces Breakthrough CPU Architecture for General-Purpose Computing, With

en-us

PLoRA: An NDP-Enhanced Pooled-Memory System for...

Condor Currents ·

2026/08/06

## Episode SummaryIn this episode, we cover: - **PLoRA: An NDP-Enhanced Pooled-Memory System for Cost-Efficient Multi-LoRA Serving** (arXiv) - **Breaking Memory Bottlenecks in Quantum Control Systems for More Precise Experiments and Higher Throughput Computing** (arXiv) - **SpacemiT K3 “16-core” RISC-V SoC system information and (early) benchmarks - CNX Software** (google_riscv) - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - phoronix.com** (google_riscv) -

en-us

Architectural Implications of Agentic AI Workflows

Condor Currents ·

2026/08/05

## Episode SummaryIn this episode, we cover: - **Architectural Implications of Agentic AI Workflows** (arXiv) - **On the Limits of Machine-Learned Ranking for Modern Microarchitectural Policies** (arXiv) - **The key CPU architecture you've never heard of: RISC-V - Red Shark News** (google_arch) - **AMD Zen 6 CPU architecture may include new optimisations to tackle game stutter - kitguru.net** (google_arch) - **NextSilicon Productizes Arbel RISC-V Core Into 64-Core Enterprise Processor - Quantum

en-us

LACE: Large Language Model Aided Multi-Agent...

Condor Currents ·

2026/08/04

## Episode SummaryIn this episode, we cover: - **LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension** (arXiv) - **A Time-Multiplexed Spiking Neural Network Accelerator with Pipelined Readout for FPGA Inference** (arXiv) - **RISC-V vs ARM: Which Instruction Set Architecture Will Dominate the Future? - Electropages** (google_arch) - **Performance aware shared memory hierarchy model for multicore processors - Nature** (google_arch) - **Bit-Brick K1: Raspberry

en-us

Themis: Software-Defined Hardware Prefetching

Condor Currents ·

2026/08/03

## Episode SummaryIn this episode, we cover: - **Themis: Software-Defined Hardware Prefetching** (arXiv) - **Beyond Static Policies: Dynamic Selection Among Modern Microarchitectural Policies** (arXiv) - **AMD Zen 6 CPU architecture may include new optimisations to tackle game stutter - KitGuru** (google_arch) - **Migration Using Context Cache for Multicore RISC‐V Processor - Wiley Online Library** (google_riscv) - **QuMA: Researchers Develop Quantum Microarchitecture that "Bridges the Gap" in

en-us

Selective KV Cache Protection for Noise-Resilient LLM...

Condor Currents ·

2026/08/02

## Episode Summary In this episode, we cover: - **Selective KV Cache Protection for Noise-Resilient LLM Inference on Analog Compute-In-Memory Systems** (arXiv) - **WitCert: Sound Runtime Risk Observability and Gating for KV-Cache Quantization** (arXiv) - **Evaluating and Calibrating Performance On RISC-V Vector Processors (KTH, LLNL, BSC) - Semiconductor Engineering** (google_riscv) - **RISC-V Mentorship Taught Me the RISC-V ISA Is Far More Than a Reference Manual** (riscv_news) - **Zhihe A210

en-us

Windowed-MTP: Removing the Full-Context Draft-KV Tax...

Condor Currents ·

2026/08/01

## Episode SummaryIn this episode, we cover: - **Windowed-MTP: Removing the Full-Context Draft-KV Tax at Million-Token Context** (arXiv) - **A Heterogeneous Neural Network Accelerator for End-to-End Multitask RF Signal Recognition** (arXiv) - **Checking In On The ISA Wars And Its Impact On CPU Architectures - Hackaday** (google_arch) - **Support RAJA and Scientific Applications on RVV Architectures** (riscv_news) - **AheadComputing Introduces Breakthrough CPU Architecture for General-Purpose

en-us

A Photonic-CXL Memory Appliance for Scalable KV Cache...

Condor Currents ·

2026/07/31

## Episode Summary In this episode, we cover: - **A Photonic-CXL Memory Appliance for Scalable KV Cache Management in LLM Inference** (arXiv) - **SPARC: Automated Root-Cause Analysis of Pre-Silicon Power Side-Channel Leakage in the Processor Design Flow** (arXiv) - **RISC-V Targets Data Centers as Open ISA Pushes Beyond Embedded Systems - eetasia.com** (google_riscv) - **Openchip unveils BER10 RISC-V processor as Europe pursues greater digital sovereignty - New Electronics** (google_riscv) - **AI is

en-us

PIMID: A Full-System Simulator with Intricacy and...

Condor Currents ·

2026/07/30

## Episode SummaryIn this episode, we cover: - **PIMID: A Full-System Simulator with Intricacy and Diversity for Processing-in-Memory** (arXiv) - **Hardware-Software Co-Design for Float16 On-Device Training on RISC-V Single-Core** (arXiv) - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - Phoronix** (google_riscv) - **RISC-V vs ARM: Which Instruction Set Architecture Will Dominate the Future? - electropages.com** (google_arch) - **Using a Performance Model to

en-us

Investigating reservoir computing for branch...

Condor Currents ·

2026/07/29

## Episode SummaryIn this episode, we cover: - **Investigating reservoir computing for branch predictionin pipelined processors using emerging CMOS memristor devices** (arXiv) - **PortLBM: A Portable Lattice Boltzmann Tool Leveraging SYCL on AMD, NVIDIA, and Intel GPUs** (arXiv) - **RISC-V: The Open-Source Revolution in CPU Architecture - design-reuse.com** (google_arch) - **RISC-V Targets Data Centers as Open ISA Pushes Beyond Embedded Systems - EE Times Asia** (google_riscv) - **RISC-V Targets

en-us

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