Condor Currents

RISC-V: The Open-Source Revolution in CPU...

Condor Currents ·

2026/07/08

## Episode Summary In this episode, we cover: - **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_arch) - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - AOL.com** (google_riscv) - **How Did An AI Agent Build a RISC V CPU Core In Just 12 Hours - IEEE Spectrum** (google_riscv) - **Zhihe A210 octa-core RISC-V SoC with 12 TOPS NPU powers SoM-based development board - CNX Software** (google_riscv) - **Modder builds

en-us

TileLens: Efficiently Using Large-Granularity Memory...

Condor Currents ·

2026/07/07

## Episode Summary In this episode, we cover: - **TileLens: Efficiently Using Large-Granularity Memory Systems with Transparent Two-Dimensional Memory Layout** (arXiv) - **Bounded-Memory Parallel Image Pulling for Large Container Images** (arXiv) - **AheadComputing Introduces Breakthrough CPU Architecture for General-Purpose Computing, With Jim Keller on Board - TechPowerUp** (google_arch) - **Deja Vu: A Brief History of Every Mac CPU Architecture - How-To Geek** (google_arch) - **Arm Neoverse

en-us

A Reconfigurable and Representation-Adaptive...

Condor Currents ·

2026/07/06

## Episode Summary In this episode, we cover: - **A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration** (arXiv) - **ELiTeFormer: An Efficient Transformer for FPGAs** (arXiv) - **The key CPU architecture you've never heard of: RISC-V - RedShark News** (google_arch) - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - Phoronix** (google_riscv) - **Memory wall: Why cache miss tolerance defines CPU performance now - EDN - Voice

en-us

A Multi-Dimensional, Per-Pass Empirical Study of the...

Condor Currents ·

2026/07/05

## Episode Summary In this episode, we cover: - **A Multi-Dimensional, Per-Pass Empirical Study of the LLVM Optimization Pipeline** (arXiv) - **Approximate Attention Weighting for Sustainable FPGA-Based Vision Transformer Inference** (arXiv) - **Performance aware shared memory hierarchy model for multicore processors - Nature** (google_arch) - **RISC-V vs ARM: Which Instruction Set Architecture Will Dominate the Future? - Electropages** (google_arch) - **Bit-Brick K1: Raspberry Pi 5 alternative with

en-us

The Fourth-Root Complexity of Data Movement

Condor Currents ·

2026/07/04

## Episode Summary In this episode, we cover: - **The Fourth-Root Complexity of Data Movement** (arXiv) - **Dynamic Ultrasound Beamforming Using Left-to-Right Arithmetic Adders on FPGA** (arXiv) - **Migration Using Context Cache for Multicore RISC‐V Processor - Wiley Online Library** (google_riscv) - **QuMA: Researchers Develop Quantum Microarchitecture that "Bridges the Gap" in Processor System Stacks - IEEE Computer Society** (google_arch) - **NextSilicon Productizes Arbel RISC-V Core Into 64-Core

en-us

RISC-V Mentorship Taught Me the RISC-V ISA Is Far...

Condor Currents ·

2026/07/03

## Episode Summary In this episode, we cover: - **RISC-V Mentorship Taught Me the RISC-V ISA Is Far More Than a Reference Manual** (riscv_news) - **RISC-V set to announce 25% market penetration — open-standard ISA is ahead of schedule, securing fast-growing silicon footprint - Tom's Hardware** (google_riscv) - **Synergy Quantum Unveils Quantum-Safe Silicon IP Cores for RISC-V-Based SoCs - The Tribune** (google_riscv) - **CPU Instruction Set Architecture (ISA) Market - Market Growth Reports**

en-us

3DLS: A 3D Logic-Stacked Architecture for...

Condor Currents ·

2026/07/02

## Episode Summary In this episode, we cover: - **3DLS: A 3D Logic-Stacked Architecture for Disaggregated LLM Serving** (arXiv) - **KernelSight-LM: A Kernel-Level LLM Inference Simulator** (arXiv) - **Checking In On The ISA Wars And Its Impact On CPU Architectures - Hackaday** (google_arch) - **Support RAJA and Scientific Applications on RVV Architectures** (riscv_news) - **Synergy Quantum Unveils Quantum-Safe Silicon IP Cores for RISC-V-Based SoCs - PR Newswire** (google_riscv) --- *Sponsored by

en-us

High-Performance NTT Accelerators for PQC leveraging...

Condor Currents ·

2026/07/01

## Episode Summary In this episode, we cover: - **High-Performance NTT Accelerators for PQC leveraging Unified Redundant Arithmetic and Fine-Tuned Microarchitecture** (arXiv) - **KernelSight-LM: A Kernel-Level LLM Inference Simulator** (arXiv) - **SpacemiT K3 “16-core” RISC-V SoC system information and (early) benchmarks - CNX Software** (google_riscv) - **Sipeed launches K3 Pico-ITX and CoM260 boards with SpacemiT RISC-V SoC - LinuxGizmos.com** (google_riscv) - **Codasip Shifts Focus to

en-us

TraceLab: Characterizing Coding Agent Workloads for...

Condor Currents ·

2026/06/30

## Episode Summary In this episode, we cover: - **TraceLab: Characterizing Coding Agent Workloads for LLM Serving** (arXiv) - **Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon** (arXiv) - **RISC-V Soft Processor System on DE10-Lite - Hackster.io** (google_riscv) - **Now you can put a SpacemiT K3 RISC-V processor in a Framework Laptop 13 - Liliputing** (google_riscv) - **Current RISC-V CPUs Being Too Slow Causes Headaches For Fedora: ~5x Slower

en-us

HBM Is Not All You Need: Efficient Disaggregated LLM...

Condor Currents ·

2026/06/29

## Episode Summary In this episode, we cover: - **HBM Is Not All You Need: Efficient Disaggregated LLM Serving across Memory-heterogeneous Accelerators** (arXiv) - **TraceLab: Characterizing Coding Agent Workloads for LLM Serving** (arXiv) - **Zhihe A210 octa-core RISC-V SoC with 12 TOPS NPU powers SoM-based development board - CNX Software** (google_riscv) - **Using a Performance Model to Implement a Superscalar CVA6** (riscv_news) - **Open-Source RISC-V Platform Trains Chip Designers From RTL To

en-us

CrossPool: Efficient Multi-LLM Serving for Cold MoE...

Condor Currents ·

2026/06/28

## Episode Summary In this episode, we cover: - **CrossPool: Efficient Multi-LLM Serving for Cold MoE Models through KV-Cache and Weight Disaggregation** (arXiv) - **Phase Matters: Characterizing Heterogeneous Vision-Language Inference on a Mobile SoC** (arXiv) - **AI is stress-testing processor architectures and RISC-V fits the moment - EDN - Voice of the Engineer** (google_riscv) - **Milk-V Jupiter2 is mini PC with a SpacemiT K3 RISC-V processor - Liliputing** (google_riscv) - **SpacemiT to launch

en-us

SOLAR: AI-Powered Speed-of-Light Performance Analysis

Condor Currents ·

2026/06/27

## Episode Summary In this episode, we cover: - **SOLAR: AI-Powered Speed-of-Light Performance Analysis** (arXiv) - **Accelerating Disaggregated RL for Visual Generative LLMs with Diffusion-Based Parallelism and Trainer-Assisted Generation** (arXiv) - **Security Researchers Find Current RISC-V CPU Implementations Coming Up Short - Phoronix** (google_riscv) - **SiFive Upgrades P500 RISC-V IP Cores - embedded.com** (google_riscv) - **Alibaba Enters The Semiconductor Market, Unveils Its First RISC-V

en-us

The Serialized Bridge: Understanding and Recovering...

Condor Currents ·

2026/06/26

## Episode Summary In this episode, we cover: - **The Serialized Bridge: Understanding and Recovering LLM Serving Performance under Blackwell GPU Confidential Computing** (arXiv) - **Learning Filters with Certainty** (arXiv) - **India Launches DHRUV64, Its First 1 GHz, 64-bit Dual-Core RISC-V CPU - TechPowerUp** (google_riscv) - **Prompt to tape out: Autonomous AI agent builds 1.5 GHz RISC-V CPU - Adafruit** (google_riscv) - **The next RISC-V processor frontier: AI - EDN - Voice of the Engineer**

en-us

CVA6-RT: an Open-Source Time-Predictable RV64...

Condor Currents ·

2026/06/25

## Episode Summary In this episode, we cover: - **CVA6-RT: an Open-Source Time-Predictable RV64 Processor for Mixed-Criticality Systems** (arXiv) - **Residual GPU Cache State on Apple M4 Pro** (arXiv) - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - Business Wire** (google_riscv) - **India unveils a homegrown dual-core 1GHz RISC-V processor, the DHRUV64 - The Register** (google_riscv) - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core

en-us

Cache-Resident LLM Inference in GB-Scale Last-Level...

Condor Currents ·

2026/06/24

## Episode Summary In this episode, we cover: - **Cache-Resident LLM Inference in GB-Scale Last-Level Caches** (arXiv) - **Energy-Efficient CNN Acceleration with MSDF Digit-Serial Arithmetic on FPGA** (arXiv) - **The RISC-V Vector Extensions for AI - Jon Peddie Research** (google_riscv) - **China's LineShine tops supercomputer ranking with all-CPU architecture - China Daily** (google_arch) - **How RISC-V CPUs and GPUs Are Reshaping High-Performance SoCs in 2026 - News and Statistics - IndexBox**

en-us

CrossPool: Efficient Multi-LLM Serving for Cold MoE...

Condor Currents ·

2026/06/23

## Episode Summary In this episode, we cover: - **CrossPool: Efficient Multi-LLM Serving for Cold MoE Models through KV-Cache and Weight Disaggregation** (arXiv) - **2.5D Root of Trust: Securing the Chiplet Ecosystem** (arXiv) - **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_arch) - **Zhihe A210 octa-core RISC-V SoC with 12 TOPS NPU powers SoM-based development board - CNX Software** (google_riscv) - **How Did An AI Agent Build a RISC V CPU Core In Just 12

en-us

Non-Uniform L2 Cache Latency Across the Streaming...

Condor Currents ·

2026/06/22

## Episode Summary In this episode, we cover: - **Non-Uniform L2 Cache Latency Across the Streaming Multiprocessors of an NVIDIA L40** (arXiv) - **MOCAP: Wafer-Scale-Chip-Oriented Memory-Orchestrated Chunked Pipelining Framework for Prefill-Only LLM Inference** (arXiv) - **Software to Silicon With RISC-V for Physical AI** (eetimes) - **Deja Vu: A Brief History of Every Mac CPU Architecture - How-To Geek** (google_arch) - **Synergy Quantum Unveils Quantum-Safe Silicon IP Cores for RISC-V-Based SoCs -

en-us

UltraQuant: 4-bit KV Caching for Context-Heavy Agents

Condor Currents ·

2026/06/21

## Episode Summary In this episode, we cover: - **UltraQuant: 4-bit KV Caching for Context-Heavy Agents** (arXiv) - **Fractional Verkle Trees: A Hypertree Decomposition and Verified Proof Serialization Architecture for High-Performance Blockchain State Accumulators** (arXiv) - **The key CPU architecture you've never heard of: RISC-V - RedShark News** (google_arch) - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - Phoronix** (google_riscv) - **AheadComputing Introduces

en-us

Low-Energy Reduced RISC-V Instruction Subset...

Condor Currents ·

2026/06/20

## Episode Summary In this episode, we cover: - **Low-Energy Reduced RISC-V Instruction Subset Processor for Tsetlin Machine Inference at the Edge** (arXiv) - **From the NYU Ultracomputer to Modern Exascale: A Historical and Architectural Survey of In-Network Computing and Scalable Synchronization** (arXiv) - **Performance aware shared memory hierarchy model for multicore processors - Nature** (google_arch) - **RISC-V vs ARM: Which Instruction Set Architecture Will Dominate the Future? -

en-us

AIA: A Customized Multi-core RISC-V SoC for Discrete...

Condor Currents ·

2026/06/19

## Episode SummaryIn this episode, we cover: - **AIA: A Customized Multi-core RISC-V SoC for Discrete Sampling Workloads in 16 nm** (arXiv) - **AIA: A 16nm Multicore SoC for Approximate Inference Acceleration Exploiting Non-normalized Knuth-Yao Sampling and Inter-Core Register Sharing** (arXiv) - **Migration Using Context Cache for Multicore RISC‐V Processor - Wiley Online Library** (google_riscv) - **The Evolution of CPU Architectures – From Intel 4004 To Modern SoCs - Wccftech** (google_arch) -

en-us

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