Condor Currents

SnakeCharmer: Orchestrating Utility, Timeliness, and...

Condor Currents ·

2026/10/23

## Episode SummaryIn this episode, we cover: - **SnakeCharmer: Orchestrating Utility, Timeliness, and Placement in GPU Prefetching** (arXiv) - **Reorienting the Vector Axis: Restructuring FlashAttention for Long-Vector Processors** (arXiv) - **Chinese chipmakers roll out new RISC-V server CPUs for AI demand - Global Times** (google_riscv) - **DAMO Academy's XuanTie E908A Is an Automotive RISC-V CPU IP Aimed at ASIL-B and ASIL-D Designs - Pandaily** (google_riscv) - **Design of a low-power RISC-V

en-us

HAWK: Heterogeneity-Aware KV Cache Transfer for...

Condor Currents ·

2026/10/22

## Episode SummaryIn this episode, we cover: - **HAWK: Heterogeneity-Aware KV Cache Transfer for Efficient GPU-NPU Phase-Disaggregated LLM Inference** (arXiv) - **Accelerating CPU Speculative Decoding via Unified Graph Execution and Transactional KV Isolation** (arXiv) - **Why Chip Design AI Benchmarks Must Go Beyond Functional Correctness** (eetimes) - **SpacemiT V100: New RISC-V Server Processor Combines 46 Cores, DDR5 and PCIe 5.0 - igor´sLAB** (google_riscv) - **Alibaba unveils automotive

en-us

PAGE404: Breaking GPU Isolation Through...

Condor Currents ·

2026/10/21

## Episode SummaryIn this episode, we cover: - **PAGE404: Breaking GPU Isolation Through Hardware-assisted Page Migration** (arXiv) - **MemLLM: End-to-end In-Storage Acceleration of On-device Retrieval-Augmented Generation using Precomputed KV Caches** (arXiv) - **Linux 7.2-rc2 Raising The Default RISC-V 64-bit CPU Limit To 256 Cores - Phoronix** (google_riscv) - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - TechPowerUp** (google_riscv) -

en-us

HBFSim: A Simulator for Exploring HBF in Memory...

Condor Currents ·

2026/10/20

## Episode SummaryIn this episode, we cover: - **HBFSim: A Simulator for Exploring HBF in Memory Hierarchies for LLMs** (arXiv) - **A Hybrid GPU and Processing-Near-Memory Architecture with Shared DRAM for Efficient Prefill-Decode Disaggregation** (arXiv) - **RISC-V extensions for high performance embedded computing ... - eeNews Europe** (google_riscv) - **Server-class 46-core RISC-V CPU runs mainstream Linux - LinuxGizmos.com** (google_riscv) - **SpacemiT V100 processor: 46-core RISC-V server -

en-us

Checking In On The ISA Wars And Its Impact On CPU...

Condor Currents ·

2026/10/19

## Episode SummaryIn this episode, we cover: - **Checking In On The ISA Wars And Its Impact On CPU Architectures - Hackaday** (google_arch) - **RISC-V vs ARM: Which Instruction Set Architecture Will Dominate the Future? - Electropages** (google_arch) - **Nvidia Vera CPU Architecture: Max single-threaded CPU at scale for agents - GamesBeat** (google_arch) - **SpacemiT Announces The V100 Server-Class RISC-V Processor - Phoronix** (google_riscv) - **RISC-V Soft Cores Go 64-Bit With Efinix Sapphire

en-us

FORGE: Procedural Weight Generation for Sparse MoE...

Condor Currents ·

2026/10/18

## Episode SummaryIn this episode, we cover: - **FORGE: Procedural Weight Generation for Sparse MoE Inference** (arXiv) - **AlignPred: Error-Controlled KV Cache Compression via Alignment and Predictive Coding** (arXiv) - **Deja Vu: A Brief History of Every Mac CPU Architecture - How-To Geek** (google_arch) - **Design Conductor: An agent autonomously builds a 1.5 GHz Linux-capable RISC-V CPU - alphaXiv** (google_riscv) - **Efinix Announces New Sapphire RV64 SoC, Bringing 64-Bit RISC-V Performance to

en-us

Foundations of Hardware-Software Leakage Contracts

Condor Currents ·

2026/10/17

## Episode Summary In this episode, we cover: - **Foundations of Hardware-Software Leakage Contracts** (arXiv) - **PAGE404: Breaking GPU Isolation Through Hardware-assisted Page Migration** (arXiv) - **The Evolution of CPU Architectures – From Intel 4004 To Modern SoCs - Wccftech** (google_arch) - **QuMA: Researchers Develop Quantum Microarchitecture that "Bridges the Gap" in Processor System Stacks - IEEE Computer Society** (google_arch) - **RISC-V Soft Processor System on DE10-Lite - Hackster.io**

en-us

Top-Down Microarchitecture Analysis Without Causal...

Condor Currents ·

2026/10/16

## Episode SummaryIn this episode, we cover: - **Top-Down Microarchitecture Analysis Without Causal Modelling Is Dangerous!** (arXiv) - **Minimum RISC-V: Maximum FPGA Efficiency** (arXiv) - **The key CPU architecture you've never heard of: RISC-V - Red Shark News** (google_arch) - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - Phoronix** (google_riscv) - **Performance aware shared memory hierarchy model for multicore processors - Nature**

en-us

TALU: A Reconfigurable Tiled-ALU Grid for RISC-V

Condor Currents ·

2026/10/15

## Episode SummaryIn this episode, we cover: - **TALU: A Reconfigurable Tiled-ALU Grid for RISC-V** (arXiv) - **CacheSmith: Accurate RAG Serving under Latency SLOs with Adaptive KV Reuse** (arXiv) - **Nuvacore’s WarpCore Ditches The ISA-First Playbook, Building CPU Silicon Before Deciding On x86, Arm, Or RISC-V - Wccftech** (google_riscv) - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - Business Wire** (google_riscv) - **Meta’s Muse AI Agent Just

en-us

Programmable Data Layouts via On-The-Fly Data...

Condor Currents ·

2026/10/14

## Episode SummaryIn this episode, we cover: - **Programmable Data Layouts via On-The-Fly Data Transformation** (arXiv) - **Simulate Before You Scale: High-Fidelity LLM Inference Planning Without GPUs** (arXiv) - **China's LineShine tops supercomputer ranking with all-CPU architecture - China Daily** (google_arch) - **Zhihe A210 octa-core RISC-V SoC with 12 TOPS NPU powers SoM-based development board - CNX Software** (google_riscv) - **Security Researchers Find Current RISC-V CPU Implementations

en-us

Read What Matters: Query-Adaptive Quantization for KV...

Condor Currents ·

2026/10/13

## Episode SummaryIn this episode, we cover: - **Read What Matters: Query-Adaptive Quantization for KV Caches** (arXiv) - **A Pipelined FPGA Architecture for Banded Sparse Matrix Dense Matrix Multiplication in Longformer** (arXiv) - **Bit-Brick K1: Raspberry Pi 5 alternative with different CPU architecture, M.2 and PCIe support launches - Notebookcheck** (google_arch) - **AheadComputing Introduces Breakthrough CPU Architecture for General-Purpose Computing, With Jim Keller on Board - TechPowerUp**

en-us

CacheFlex: Direct Software-Managed Access to...

Condor Currents ·

2026/10/12

## Episode SummaryIn this episode, we cover: - **CacheFlex: Direct Software-Managed Access to Higher-Level Cache for Scalable Vector Support** (arXiv) - **Taking Tokenization off the Host for Agentic LLM Serving** (arXiv) - **For Automakers, RISC-V Isn’t Just About Ownership: It’s About Freedom of Choice** (riscv_news) - **What Is a Microarchitecture? Understanding Processors and Register Files in an ARM Core - All About Circuits** (google_arch) - **Armaan Gomes and Friends Deliver Playable Doom on

en-us

A Framework for Accelerating Transformer Inference on...

Condor Currents ·

2026/10/11

## Episode SummaryIn this episode, we cover: - **A Framework for Accelerating Transformer Inference on RISC-V for Edge AI** (arXiv) - **ECO: Energy-Oriented Configuration Optimization for Attention FFN Disaggregated LLM Serving** (arXiv) - **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_arch) - **The key CPU architecture you've never heard of: RISC-V - RedShark News** (google_arch) - **Efinix Goes 64-Bit with Its Latest Sapphire SoC FPGA Cores, Based on the

en-us

SUSpMV: A High Frequency Sparse Matrix Vector...

Condor Currents ·

2026/10/10

## Episode Summary In this episode, we cover: - **SUSpMV: A High Frequency Sparse Matrix Vector Multiplier on HBM Enabled FPGA written in SUS** (arXiv) - **BenchmarkAnything: Agent-Driven Construction of Simulator-Ready Microarchitecture Benchmarks** (arXiv) - **Nuvia Architects’ New CPU Core Can Use Arm, RISC-V or x86 - HWCooling.net** (google_riscv) - **Upbeat Technology’s Bluemag Pi Pairs RISC-V Processors and AI Inference for Advanced Flight Control - Embedded Computing Design** (google_riscv) -

en-us

CacheFit: The Rising Cost of Cache Replacement and...

Condor Currents ·

2026/10/09

## Episode SummaryIn this episode, we cover: - **CacheFit: The Rising Cost of Cache Replacement and Constraint-Driven Redesign of Last-Level Cache Replacement Policies** (arXiv) - **CXDVirt: Low Latency Kernel Module Based CXL-SSD Emulation** (arXiv) - **Nuvia’s Architects Now Preparing a CPU for Arm, RISC-V or x86 - HWCooling.net** (google_riscv) - **Openchip unveils BER10 RISC-V processor as Europe pursues greater digital sovereignty - New Electronics** (google_riscv) - **Enabling Comprehensive

en-us

CHiRP: Control-Flow History Reuse Prediction

Condor Currents ·

2026/10/08

## Episode SummaryIn this episode, we cover: - **CHiRP: Control-Flow History Reuse Prediction** (arXiv) - **SVRF: Efficient Register Storage for Long-Vector Architectures** (arXiv) - **WheatForce: Learning From CPU Architecture Mistakes - Hackaday** (google_arch) - **Efinix Sapphire RV64 SoC – Configurable RISC-V soft-cores with DDR3, LPDDR4x, and HyperRAM for Efinix FPGAs - CNX Software** (google_riscv) - **RISC-V Processor Advances Local Chip Design - Open Source For You**

en-us

Trail: Scalable and Low-Cost Temporal TLB Prefetching...

Condor Currents ·

2026/10/07

## Episode SummaryIn this episode, we cover: - **Trail: Scalable and Low-Cost Temporal TLB Prefetching via Page-Table-Embedded Deltas** (arXiv) - **CACHEFORGE: LLM-Guided End-to-End Generative Cache Replacement Policy for Performance and Hardware Efficiency** (arXiv) - **Efinix Adds 64-Bit RISC-V SoC with Linux and DDR Support - www.embedded.com** (google_riscv) - **RISC-V CPU Performance Up 8x In Five Years: SiFive HiFive Unmatched To SpacemiT K3 - Phoronix** (google_riscv) - **Prompt to tape out:

en-us

Characterizing High Bandwidth Flash for LLM Serving

Condor Currents ·

2026/10/06

## Episode SummaryIn this episode, we cover: - **Characterizing High Bandwidth Flash for LLM Serving** (arXiv) - **Request Order Matters: Cache-History Sensitivity in Selective KV-Cache Reuse for Rolling Agents** (arXiv) - **Design of a low-power RISC-V based intelligent endoscopy detection processor: EndoRISC-V - Nature** (google_riscv) - **Your Nvidia GPU has dozens of RISC-V cores inside it, and one of them took over a huge part of the graphics driver - XDA** (google_riscv) - **Efinix Announces

en-us

ServeTwin: A Benchmark-Validated Simulator for...

Condor Currents ·

2026/10/05

## Episode SummaryIn this episode, we cover: - **ServeTwin: A Benchmark-Validated Simulator for Distributed LLM Architecture Exploration** (arXiv) - **AdaptViT: Runtime-Adaptive Vision Transformer Deployment on Custom RISC-V** (arXiv) - **RISC-V extensions for high performance embedded computing ... - eeNews Europe** (google_riscv) - **Efinix Adds 64-Bit RISC-V SoC for FPGA-Based Embedded Systems - EE Times Asia** (google_riscv) - **Efinix Adds 64-Bit RISC-V SoC with Linux and DDR Support -

en-us

Where Activation Sparsity and KV-Cache Sparsity Cross...

Condor Currents ·

2026/10/04

## Episode SummaryIn this episode, we cover: - **Where Activation Sparsity and KV-Cache Sparsity Cross in LLM Decoding** (arXiv) - **U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC** (arXiv) - **Checking In On The ISA Wars And Its Impact On CPU Architectures - Hackaday** (google_arch) - **How Did An AI Agent Build a RISC V CPU Core In Just 12 Hours - spectrum.ieee.org** (google_riscv) - **Zhihe A210 octa-core RISC-V SoC with 12 TOPS NPU powers SoM-based development

en-us

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